1. Technical Field
This invention relates to logic circuits, and more particularly to digitally configurable sequential logic circuits for serial bit pattern generation.
2. Discussion
A serial binary pattern generator is a sequential logic circuit which produces a sequence of binary values at its output. The bits which make up the sequence appear at the output of the circuit serially, one bit per cycle of the input clock.
There is a nearly infinite variety of binary sequences which can be produced by sequential logic circuits. One particularly useful kind of sequence is one defined here as "maximally spread." Every finite sequence of bits contains some number of ones and some number of zeros. A maximally spread sequence of bits has the property that if one constructs an infinite sequence by laying copies of the finite sequence end to end along a line in both directions infinitely, all the ones in the infinite sequence are as far apart from each other as possible, and all the zeros in the infinite sequence are as far apart from each other as possible. For example if there are an equal number of ones and zeros in the finite sequence, then the ones and zeros would alternate: "...1010101010..." If there are 3 ones for every 5 zeros in the finite sequence then the maximally spread sequence would be: "...1001001010010010..." No rearrangement of the ones and zeros in such a sequence would separate the ones from each other any better, or separate the zeros from each other any better.
A device is digitally configurable if its operation can be modified by changing the value of one or more digital words presented to the device as control values.
Given these definitions, the present invention is a digitally configurable serial binary pattern generator which produces maximally spread binary sequences at its output. Such a device has a variety of applications. The following paragraphs describe three such applications. They are: clock division by rational numbers, data stuffing, and precision duty cycle generation.
Logic circuits are used in a variety of electronic and computer applications to perform various functions. Typically, each component of a logic circuit requires a clock input to trigger the execution of the component's logic routine. Currently various high rate digital clocks are available. It sometimes becomes necessary or desirable to generate synchronous lower rate clocks by "dividing" an available high rate source clock. This can be accomplished with simple logic if the ratio of the source clock frequency to the desired clock frequency is an even integer, (e.g., dividing a 20 kHz source clock by 4 to produce a desired 5 kHz clock). Division by an even integer is a simple case because a fixed integer number of source clock periods separate successive leading and trailing edges of the desired clock signal. However if the ratio of the source clock frequency to the desired clock frequency is an odd integer or not an integer at all then generation of the desired synchronous, lower frequency clock is more difficult. For the case where the ratio of the source to desired clock frequencies can be expressed as the ratio of two positive integers, the present invention can be combined with simple external circuitry to produce the best all-digital approximation to the desired clock. The clock so produced will have the same average frequency (leading edges per second) as a 50% duty cycle clock of the desired frequency, but its leading and trailing edges will always be coincident with leading edges of the source clock. Such a clock signal is acceptable in most digital circuits and essential in some. Traditionally, the production of such a clock involves the use of analog frequency synthesizers. That approach brings with it all the attendant difficulties in mixing analog and digital circuits especially with respect to synchronization requirements.
In a variety of digital data communication circuits, the allowable input data rate of a device is constrained to be among a small set of rates, e.g., 25, 50, and 100 Mbps. When it is desired to transmit data from a digital source whose rate is not in the allowed set, the source data can be "stuffed" with extraneous data to bring the combined rate up to an allowable rate. For example, a 47 Mbps data source could be stuffed with 3 Mbps of extraneous data to produce a combined data rate of 50 Mbps. Such a scheme is only practical if the extraneous data can later be filtered out. Perhaps the simplest scheme for mixing the two data streams is to send, e.g., 47 "data bits" followed by 3 "stuff bits." However, to minimize the required bandwidth of the circuitry involved, it is desirable to spread out the stuff bits as much as possible within the data bits. For example, send 47 data bits and 3 stuff bits in the following order: 16 data bits, 1 stuff bit, 16 data bits, 1 stuff bit, 15 data bits, 1 stuff bit. The use of a digitally configurable device which could produce such a repeatable, "maximally spread" stuff/data bit pattern for a wide range of stuff/data rate ratios would give a great deal of flexibility.
It is sometimes desired to produce a binary signal with a known duty cycle. If a duty cycle of M/N is desired, a simple way to accomplish this is to hold an output signal high for M clock cycles and low for N-M clock cycles. If the M clock cycles during which the output is high are spread out as described above among the N-M clock cycles during which the output is low, then the instantaneous deviation of the output signal's duty cycle from the desired duty cycle is minimized. Such a signal could, for example, be applied to a low-pass filter to produce a precision DC voltage equal to M/N times a precision reference voltage. If M and N are digitally programmable then the output from such a circuit will be a digitally programmable precision voltage.